Jialin Zheng is a Research Scientist at Princeton University and was previously a Postdoctoral Research Associate at Purdue University. He received his Ph.D. in Electrical Engineering from Tsinghua University.
His research focuses on AI-driven design and control of intelligent circuits and complex networked systems, spanning applications from integrated microwave communication to megawatt-scale power conversion and transfer. He develops advanced digital methodologies to enable scalable, high-performance circuit and integrated infrastructures across both information and power domains.
PhD in Electrical Engineering, 2024
Tsinghua University
BEng in Electrical Engineering, 2019
Beijing Jiaotong University
Check out my projects below.

A unified ML framework—Event-Automata + Physics-Embedded Neural ODEs + Neural Substitute Solver—for accurate, real-time inference of hybrid (continuous–discrete) dynamics with reliable Sim-to-Real transfer to edge hardware.

From multi-DOF modulation and universal phase-shift control to device-aware electro-thermal modeling and CDT-MPC, this project delivers efficient, soft-switching, and control-ready designs for DAB/MMAB at 50–400 kHz+.

Sim-to-Real Edge Digital Twins that fuse event-aware physics with neural operators for sub-microsecond inference, online parameter self-calibration, and control integration on FPGA/MPSoC.

Event-driven HIL simulation that replaces tiny fixed steps with switching-aware sampling and variable-order solvers (SCED/DHT, VTR-CHIL, DAT/SEO), enabling high-frequency, large-scale power electronics on commodity CPUs/MPSoCs.

Event-axis, synchronization-aware co-simulation that scales CHIL/PCCO from kW MMCs to MW-level converters by key-frame prediction, event-driven data rematching, and hybrid CPU–FPGA execution—boosting fidelity and easing real-time constraints.

Network-aware multi-agent RL that scales decentralized secondary voltage control by truncating critics to κ-hop neighborhoods with provable approximation guarantees; validated up to 114 DGs.

Deterministic sub-µs FPGA solvers (12.5–75 ns) combining semi-implicit leapfrog, topology-aware partitioning, and IMEX techniques for stability, low memory, and controller-accurate HIL.
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